The semiconductor integrated circuits have been micro-miniaturized more and more with increasing integration rate. Further, in MOS type integrated circuits, the thickness of the gate insulating film has been reduced more and more.
When the gate insulating film becomes thin, an electric field applied to the gate insulating film increases, and hence there arises the possibility that the gate will be easily damaged.
For this reason there has recently been developed a semiconductor integrated circuit such that a voltage (e.g., 5 V) supplied from the outside of the integrated circuit is deboosted to a lower voltage (e.g., 3 V) inside the integrated circuit, so that the deboosted voltage can be used as a power source voltage of an internal circuit of the integrated circuit.
Further, from the standpoint of less electricity consumption in integrated circuits, there has been developed a semiconductor memory device or a CPU in which the supply voltage of the integrated circuit itself is set at 3 V and the entire operation thereof is assured at this low voltage of 3 V.
Under such circumstances, a demand for semiconductor memory devices operated at 3 V has become strong in recent years, and such types of products are increasing gradually.
However, in the case of a non-volatile semiconductor memory device which comprises floating gate type MOS transistors as memory cells, it is difficult to reduce the operating voltage down to 3 V, since the threshold voltage of the memory cell is high.
FIG. 16 is a cross-sectional view showing a MOS transistor of floating gate structure. As is shown in FIG. 16, on P-type semiconductor substrate 131, drain 132 of an N.sup.+ diffusion region and source 133 of an N.sup.+ diffusion region are formed with channel region 134 interposed therebetween. Over channel region 134, floating gate 135 is disposed with first insulating film 137 interposed therebetween. Further, over the floating gate 135, control gate 136 is disposed with second insulating film 138 interposed therebetween.
In the construction as described above, since the first insulating film 137 is interposed between the floating gate 135 and the channel region 134, and the second insulating film 138 is interposed between the floating gate 135 and the control gate 136, a potential of the floating gate is increased when a potential is applied to the control gate 136. The channel region 134 can be controlled by the potential of the floating gate. The apparent thickness of the gate insulating film when seen from the control gate 136 to the channel region 134 is relatively thick because of the presence of both the first and second insulating films 137 and 138, with the result that the apparent threshold voltage increases when seen from the control gate 136.
Further, in the case of the NAND type EEPROM, for instance, a logic "1" or a logic "0" is stored in the memory cells in correspondence to the positive or negative threshold voltage of the memory cell. In other words, when electrons are injected into the floating gate 135, the positive threshold voltage can be obtained; and when electrons are emitted from the floating gate 135, the negative threshold voltage can be obtained. The electrons are injected from the substrate 131 to the floating gate 135 and emitted from the floating gate 135 to the substrate 131 through the first insulating film 137 by using a tunnel effect. Consequently, the threshold voltages of memory cells distribute usually within a range due to dispersion in thickness of the gate insulating film and subtle variations in the quality of the gate insulating film and a manufacturing process. FIG. 17 is a graphical representation showing the distribution of the threshold voltages of the memory cells, in which the number of memory cells is taken on the ordinate and the threshold voltage is taken on the abscissa. FIG. 17 indicates that the positive threshold voltages distribute within a range between two threshold voltages Vth1 and Vth2.
In the NAND type EEPROM, when data are read from the memory cells, the control gates 136 of the selected memory cells are set to a logic "0" and the control gates 136 of the non-selected memory cells are set to a logic "1". The memory cells of the negative threshold voltage are turned on when the control gates 136 are a logic "0", and the memory cells of the positive threshold voltage are turned off when the control gates 136 are a logic "0". The data stored in the memory cells are read on the basis of whether the selected memory cells are turned on or off.
On the other hand, the control gates 136 of the non-selected memory cells are set to a logic "1", so that the non-selected memory cells are turned on irrespective of the positive and negative threshold voltages thereof.
FIG. 18 shows an example of the circuit configuration of the NAND type EEPROM memory cells. The memory cell block 127 is constructed by connecting memory cells 31 to 34 in series between select transistor 4 and current cut-off transistor 1. In these memory cells 31 to 34, the gates of the non-selected memory cells are set to a logic "1" (a turn-on state) and the gates of the selected memory cells are set to a logic "1" (a turn-off state). Under these conditions, data stored in the selected memory cells can be read on the basis of whether the selected memory cells are turned on or off; that is, whether current flows through the series-connected memory cells 31 to 34.
However, as shown in FIG. 17, in order to turn on all the non-selected memory cells, it is necessary to apply a voltage, which is higher than the threshold voltage Vth2 of FIG. 17, to the control gate of the non-selected memory cells. If a larger current flows through the memory cells, it is possible to increase the data read speed of the semiconductor memory.
As already explained, the threshold voltages of the memory cells disperse within a range. In usual, this range (Vth2-Vth1) lies between 1 and 2 V. When a data is read from the memory cell, data of a logic "1" is generally supplied from a voltage supply terminal to the control gate of the memory cell via a row line. When the supply voltage from the voltage supply terminal is reduced, since the difference between the threshold voltage Vth2 and the supply voltage becomes small, the current of the memory cell is reduced. Consequently, the data read speed is delayed.
In contrast with this, in order to increase the difference between the threshold voltage Vth2 and the supply voltage, the threshold voltage Vth2 must be low. In this case, however, it is necessary to retain the threshold voltage Vth1 at the positive value. In other words, in order to reduce the threshold voltage Vth2 under the condition that the threshold voltage Vth1 is kept at the positive value, it is necessary to reduce the dispersion range (Vth2-Vth1) of the threshold voltage. However, this is rather difficult from the standpoint of the manufacturing process technique.
Instead of the above-mentioned method, for instance it is also possible to consider that the supply voltage is boosted inside the integrated circuit and then the boosted voltage is applied to the control gates of the non-selected memory cells. In this case, however, since the booster circuit is usually small in the current supply capability, there exists such a drawback that it takes a long time to charge the row lines.
FIG. 19 is a block diagram showing the relationship between the memory cell array and the row decoder of a NAND type EEPROM. As shown in FIG. 19, the gate of the select transistor 4, the gate of the current cut-off transistor 1, and the gates of the memory cells 31, 32, 33, . . . are connected to row line W. Between column line 128 and a reference potential, memory cell block 127; that is, a series-connected circuit composed of select transistor 4, the memory cells 31, 32, 33, . . . , and current cut-off transistor 1 is connected. Further, a plurality of the memory cell blocks 127 are arranged into a matrix array. One end of the select transistor 4; that is, one end of the memory cell block 127 is connected to column line 128 for each corresponding column. The column line 128 is connected to a detecting circuit (not shown) to read data from the memory cells selected by the row decoder 139.
FIG. 20 shows a part of FIG. 19 in more detail manner, in which the number of the memory cells in each memory cell block 127 is four.
As shown in FIG. 20, signal B1 of the row decoder 139 is given to the gates of P-channel transistors 51 to 54 and further to the gates of N-channel transistors 61 to 64 via an inverter I1 as signal /B1. On the other hand, signals S1 to S4 are supplied to the sources of transistors 51, 61; 52, 62; 53, 63; and 54, 64, respectively. The drains of the transistors 51 and 61 are connected to the gate of the memory cell 31 via a row line W11; the drains of the transistors 52 and 62 are connected to the gate of the memory cell 32 via a row line W12; the drains of the transistors 53 and 63 are connected to the gate of the memory cell 33 via a row line W13; and the drains of the transistors 54 and 64 are connected to the gate of the memory cell 34 via a row line W14. The row lines W11 to W14 are connected to a reference potential through the transistors 6 to 9. The signal B1 is supplied to the gates of the transistors 6 to 9, respectively. The signal /B is supplied to the select transistor 4 of the memory cell block 127 (1), and signal .phi. is supplied to the current cut-off transistor 1.
In FIG. 20, transistors 6 to 9 are N-channel type MOS transistors.
In the same way, as shown in FIG. 20, a signal B2 of the row decoder 139 is given to the gates of transistors 51 to 54 and further to the gates of transistors 61 to 64 via an inverter I2 as signal /B2. On the other hand, signals S1 to S4 are supplied to the sources of transistors 51, 61; 52, 62; 53, 63; and 54, 64, respectively. The drains of the transistors 51 and 61 are connected to the gate of the memory cell 31 via a row line W21; the drains of the transistors 52 and 62 are connected to the gate of the memory cell 32 via a row line W22; the drains of the transistors 53 and 63 are connected to the gate of the memory cell 33 via a row line W23; and the drains of the transistors 54 and 64 are connected to the gate of the memory cell 34 via a row line W24. The row lines W21 to W24 are connected to a references potential through the transistors 6 to 9, respectively. The signal B2 is supplied to the gates of the transistors 6 to 9. The signal /B2 is supplied to the select transistor 4 of the memory cell block 127 (2), and signal .phi. is supplied to the current out-off transistor 1.
FIG. 21 is a timing chart showing the voltage waveforms at the respective nodes, in which (A) shows the waveform of the signal S1; (B) shows that of the signal S2; (C) shows that of the signal S3, (D) shows that of the signal S4; (E) shows that of the signal B1; (F) shows that of the signal B2, (G) shows that of the row line W11; (H) shows that of the row line W12; (I) shows that of the row line W13; (J) shows that of the row line W14, (K) shows that of the row line W21; (L) shows that of the row line W22; (M) shows that of the row line W23; and (N) shows that of the row line W24.
The current out-off transistor 1 is controlled by the signal .phi.. The transistor 1 is turned on when data is read, and is turned off when data is written.
The memory cell block 127 is a series-connected circuit composed of a plurality of the memory cells 31 to 34, the select transistor 4 and the current cut-off transistor 1. The memory cell block 127 is selected and connected to the column line 128 by the select transistor 4.
The select transistors 4 are connected to the row lines WL10 and WL20, controlled by the signals /B1, /B2 on these row lines, respectively. For instance, when the memory cell block 127 (1) is selected, the signal B1 is set to a logic "0".
In a data read mode, as shown by (A) to (D) in FIG. 21, any one of the signals S1 to S4 is controlled so as to be set to a logic "0" and the remaining other signals are controlled to be set to a logic "1".
Now, as shown by (E) in FIG. 21, when the signal B1 is set to a logic "0", the memory cell block 127 (1) corresponding thereto is selected, and the transistors 51 to 54 and 61 to 64 are all turned on.
In this case, as shown by (F) in FIG. 21, the signal B2 is a logic "1". Accordingly, the memory block 127 (2) corresponding thereto is not selected, and the transistors 51 to 54 and 61 to 64 are all turned off.
In this case, as shown by (G), (H), (I) and (J) in FIG. 21, any one of the row lines W11 to W14 is controlled so as to be set to a logic "0" and the remaining row lines are controlled so as to set to a logic "1" on the basis of the corresponding signals S1 to S4, respectively. These signals are given to the respective control gates of the memory cells 30 to 34, respectively.
On the other hand, since the transistors 6 to 9 are all turned on by the signal B2, as shown by (K), (L), (M) and (N) in FIG. 21, the row lines W21 to W24 are all set to a logic "0".
In contrast with this, as shown by (F) in FIG. 21, when the signal B2 changes to a logic "0" at the time point t1, the memory block 127 (2) corresponding thereto is selected. Under these conditions, as shown by (E) in FIG. 21, the signal B1 changes to a logic "1", and thereby the memory cell block 127 (I) corresponding thereto is not selected.
In this case, as shown by (K), (L), (M) and (N) in FIG. 21, any one of the row lines W21 to W24 is kept at a logic "0" by the signals S1 to S4, and the other remaining lines are set to a logic "1". These signals are given to the control gates of the memory cells 31 to 34, respectively.
On the other hand, since the transistors 6 to 9 are all turned on by the signal B1, as shown by (G), (H), (I) and (J) in FIG. 21, the row lines w11 to W14 are all set to a logic "0".
As described above, it is possible to read data of the memory cell block 127 by selectively setting any one of the gates of the memory cells 31 to 34 of the selected memory block 127 to a logic "0".
Here, in FIG. 20, the case where data is read from any one of the memory cells 31 to 34 of the selected memory cell block 127 is taken into account. In this case, all the row lines other than the row lines connected to the selected memory cells must be charged. This charging is executed by the row decoder 139. In order to complete the charges of these row lines in a short time, a large current supply capability is required.
The signals S1, S2, S3, and S4 are supplied to a1 the memory cell blocks 127. So, the signals S1, S2, S3, and S4 are connected to all the corresponding transistors 51, 52, 53, 54, 61, 62, 63, and 64 of the row decoder 139 through wiring layers. And these wiring layers are arranged from one end to other end of the row decoder 139 through the row decoder 139. So, these wiring layers having a large parasitic capacitance. Consequently the signals S1, S2, S3, and S4 charge the large parasitic capacitance.
In this example shown in FIG. 20, the single memory cell block 127 is composed of four memory cells 31 to 34. In practice, however, it is general that the single memory cell block 127 is composed of 8 or 16 memory cells in order to reduce the chip size and thereby to reduce the cost thereof. For instance, in the case of the memory cell block 127 composed of 16 memory cells, since 16 signals S1, S2, . . . are required, a large charging capability is required.
However, when the integrated circuit itself is driven by a relatively low voltage and further when only the row lines are charged to a boosted voltage by a booster circuit to boost the supply voltage to a high boosted voltage, a large capacitance must be charged by an internal booster circuit (which is relatively low in the current supplying capability). Consequently, there exists such a drawback that a long time is needed to charge the row lines and thereby the data read speed is delayed. In addition, when the memory cell block 127 is shifted from the selected state to non-selected status, the charges of all the row lines must be discharged; that is, the earlier-stored charges are all disused, which is not preferable from the standpoint of power saving.